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CHAPTER 7 16-bit I/O timer
I Operation of Input Capture
• When the valid edges of the external signals input to the input pins (IN0 to IN3) are detected, the input
capture valid edge detection flag bit (ICS: ICP) corresponding to the input pin is set to 1.At the same
time, the count value of the 16-bit free-run timer is stored in the input capture data registers (IPCP)
corresponding to the input pins (IN0 to IN3).
• The edge to be detected can be selected from the rising edge, falling edge and both edges by setting the
input capture edge select bit in the input capture control status register (ICS: EG).]
• When the effective edge is detected by the input captures corresponding to the input pins (IN0 to IN3)
when the input captures corresponding to the input pins (IN0 to IN3) are enabled for interrupts, an input
capture interrupt is generated.
• The input capture valid edge detection flag bit (ICS: ICP) is set when the valid edge is detected,
regardless of the interrupt enable settings (ICS01, ICS23: ICE1, ICE0).
• Table 7.6-1 shows correspondence between input pins and input captures.
Table 7.6-1 Correspondence between Input Pins and Input Captures
Input Pin
IN0
IN1
IN2
IN3
240
Interrupt Request Flag
Bit of Input Capture
ICS01: ICP0
ICS01: ICP1
ICS23: ICP0
ICS23: ICP1
Interrupt Output
Input Capture Data
Enable Bit of Input
Capture
ICS01: ICE0
ICS01: ICE1
ICS23: ICE0
ICS23: ICE1
Register
IPCP0
IPCP1
IPCP2
IPCP3
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