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G
Procedure for Transmitting message Buffer (x)
After completion of presetting, set the message buffer (x) enabled (BVALR: BVALx =1) by message
buffer enable register.
G
Setting transmit data length code
• Set the transmit data length code (byte count) to the DLC3 to DLC0 bits in the DLC register (DLCR).
• When transmitting a data frame (TRTRR: TRTRx = 0), set the data length of the transmit message.
• When transmitting a remote frame (TRTRR: TRTRx = 1), set the data length (byte count) of the
message to be requested.
Note:
Setting other than 0000
G
Setting transmit data (only for transmission of data frame)
When transmitting a data frame (TRTRR: TRTRx = 0), set the data of byte count to be transmitted in the
data register (DTR).
Note:
Rewrite transmit data after setting the TREQx bit in the transmit request register to 0. There is
no need to set the bit disabled in the message buffer enable register (BVALR: BVALx = 0).
When the bit is set to disabled, no remote frame can be received.
G
Transmit RTR register (TRTRR)]
• When transmitting a data frame, set the TRTRx bit in the transmission RTR register to "0".
• When transmitting a remote frame, set the TRTRx bit in the transmission RTR register to "1".
G
Setting conditions for starting transmitting (only in transmitting data frame)
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmission immediately, set the RFWTx bit in the remote frame wait register to "0".
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmission after waiting until a remote frame is received (RRTRR: RRTRx = 1), set the
RFWTx bit in the remote frame wait register to "1".
Note:
When the RFWTx bit in the remote frame wait register is set to 1, no remote frame can be
transmitted.
G
Setting transmission complete interrupt
• When enabling an interrupt when transmission is completed (TCR: TCx = 1), set the TIEx bit in the
transmit complete enable register to "1".
• When disabling an interrupt when transmission is completed (TCR: TCx = 1), set the TIEx bit in the
transmission complete enable register to "0".
G
Canceling bus halt
After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
to 1000
(0 to 8 bytes) is prohibited.
B
B
CHAPTER 16 CAN controller
545
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