Timer Control Status Registers (High) (Tmcsr0: H, Tmcsr1: H) - Fujitsu MB90895 Series Hardware Manual

8.3.1 Timer Control Status Registers (High) (TMCSR0: H,
TMCSR1: H)
The timer control status registers (High) (TMCSR0: H, TMCSR1: H) set the operation
mode and count clock.
This section also explains the bit 7 in the timer control status registers (Low) (TMCSR0:
L, TMCSR1: L).
I Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
Figure 8.3-3 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
15 14
13
R/W : Read/Write
: Undefined
X
: Unused
: Reset value
8 7
12 11 10 9
R/W R/W R/W R/W R/W
MOD2 MOD1 MOD0
MOD2 MOD1 MOD0
bit11 bit10
CSL1 CSL0
T : Machine cycle
Reset value
XXXX00000
B
bit9 bit8 bit7
Operating mode select bit (internal clock mode)
(CSL1,0="00
Input pin function
Torigger disabled
0 0 0
0 0 1
Torigger input
0 1 0
0 1 1
1 0
Gate input
1 1
bit7
bit9 bit8
Operating mode select bit (Event count mode)
Input pin function
0 0
0 1
Torigger input
1 0
1 1
Count clock select bit
Count clock
0 0
0 1 Internal clock mode
1 0
Event count mode
1 1
CHAPTER 8 16-bit reload timer
"," 01
","10 ")
B B B
Valid edge, level
Rising edge
Falling edge
Both edge
"L" level
"H" level
(CSL1,0= "11 " )
B
Valid edge
Rising edge
Falling edge
Both edge
Count clock cycle
1
2 T
3
2 T
5
2 T
External event clock
255