Fujitsu MB90895 Series Hardware Manual page 503

Message buffer (DTR register)
bit15
*: Resarved area is address for using in system, so it must not use.
I Generation of Interrupt Request by CAN Controller
The CAN controller has three types of interrupts: transmit complete interrupt, receive complete interrupt,
and node status interrupt. The CAN controller generates each interrupt request as follows:
• When a transmit complete interrupt is enabled for the message buffer (x) (TIRE: TIEx = 1), the TCx bit
in the transmit complete register is set to "1" and a transmit complete interrupt request is generated after
a completion of message transmitting.
• When a receive complete interrupt is enabled for the message buffer (x) (RIRE: RIEx = 1), the RCx bit
in the receive complete register is set to "1" and a receive complete interrupt request is generated after a
completion of message receiving.
• When a node status transition interrupt is enabled (CSR: NIE = 1), the NT bit in the CAN status register
is set to "1" and a node status transition interrupt request is generated after the node status transits.
Figure 16.3-3 Registers of CAN Controller (DTR Register)
bit8 bit7
DTR0 (Data register 0) (8byte)
DTR1 (Data register 1) (8byte)
DTR2 (Data register 2) (8byte)
DTR3 (Data register 3) (8byte)
DTR4 (Data register 4) (8byte)
DTR5 (Data register 5) (8byte)
DTR6 (Data register 6) (8byte)
DTR7 (Data register 7) (8byte)
* (
Reserved area 128byte)
CHAPTER 16 CAN controller
bit0
Reset value
XXXXXXXX XXXXXXXX
B
to
XXXXXXXX XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX
XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX
XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
XXXXXXXX
XXXXXXXX
B
to
XXXXXXXX
XXXXXXXX
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
485