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I Return from Timebase Timer Mode
The timebase timer mode is cancelled by a reset factor or when an interrupt is generated.
G
Return by reset factor
When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after
the timebase timer mode is cancelled, transiting to the reset sequence.
Note:
To return from timebase timer mode to main clock mode using the external reset pin (RST
pin), input the Low level for at least 100 µs.
G
Return by interrupt
When an interrupt request higher than interrupt level (IL) 7 is generated from the watch timer, timebase
timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled.After the
timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is
identified according to the settings of the I flag in the condition code register (CCR), the interrupt level
mask register (ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the nest instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
• The following two timebase timer modes are available:
- Main clock ←→ timebase timer mode
- PLL clock ←→ timebase timer mode
Notes:
• When handling an interrupt, the CPU usually services the interrupt after executing the
instruction that follows the one specifying the timebase timer mode.
• When the CPU returns from the timebase timer mode in response to an interrupt, the CPU
services the interrupt a maximum of 80 µs after accepting the interrupt request.
CHAPTER 3 CPU
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