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CHAPTER 9 Watch timer
Table 9.3-1 Functions of Watch Timer Control Register (WTC)
bit2
to
bit0
bit3
bit4
bit5
bit6
bit7
284
bit name
WTC2, WTC1, WTC0:
These bits set the interval time of the watch timer.
Interval time select bits
•
•
WTR:
This bit clears the watch timer counter.
Watch timer clear bit
When set to "0": Clears watch timer counter to "0000
When the bit is set to "1": No effect.
Read: "1" is always read.
WTOF:
This bit is set to "1" when the counter value of the watch timer
Overflow flag bit
reaches the value set by the interval time select bit.
When an overflow occurs (WTOF = 1) with interrupt request
enabled (WTIE = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
•
WTIE:
This bit enables or disables generation of an interrupt request
Overflow interrupt
when the watch timer counter overflows (carries).
enable bit
When set to "0": Interrupt request not generated even at
overflow (WTOF = 1)
When set to 1: Interrupt request generated at overflow
(WTOF = "1")
SCE:
This bit indicates that the oscillation stabilization wait time of
Oscillation stabilization
the sub clock ends.
wait time end bit
When cleared to "0": Sub clock in oscillation stabilization
wait state
When set to "1": Sub clock oscillation stabilization wait time
ends
•
WDCS:
This bit selects the operation clock of the watchdog timer.
Watchdog clock select
<Main clock mode or PLL clock mode>
bit
When set to "0": Selects output of watch timer as operation
clock of watchdog timer.
When set to "1": Selects output of timebase timer as
operation clock of watchdog timer.
<Sub clock mode>
Always set this bit to "0" to select the output of the watch timer.
Note:
Function
When the interval time set by the WTC2 to WTC0 bits is
reached, the corresponding bit of the watch timer counter
overflows (carries) and the overflow flag bit is set (WTC:
WTOF = 1).
To set the WTC2 to WTC0 bits, set the WTOF bit to 0.
The overflow flag bit is set to 1 when the bit of the watch
timer counter corresponding to the interval time set by the
interval time select bits (WTC2 to WTC0) overflows.
The oscillation stabilization wait time of the sub clock is
14
fixed at 2
/SCLK (SCLK: sub clock frequency).
The watch timer and the timebase timer operate
asynchronously. When the WDCS bit is changed from "0" to
"1", the watchdog timer may run fast.The watchdog timer
must be cleared before and after changing the WDCS bit.
"
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