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APPENDIX
Table A.8-13 31 Branch 1 instructions
Mnemonic
BZ/BEQ
rel
2
BNZ/BNE
rel
2
BC/BLO
rel
2
BNC/BHS
rel
2
BN
rel
2
BP
rel
2
BV
rel
2
BNV
rel
2
BT
rel
2
BNT
rel
2
BLT
rel
2
BGE
rel
2
BLE
rel
2
BGT
rel
2
BLS
rel
2
BHI
rel
2
BRA
rel
2
JMP
@A
1
JMP
addr16
3
JMP
@ear
2
JMP
@eam
2+
JMPP
@ear *3
2
JMPP
@eam *3
2+
JMPP
addr24
4
CALL
@ear *4
2
CALL
addr16 *5
2+
CALL
@eam *4
3
CALLV
#vct4 *5
1
CALLP
@ear *6
2
CALLP
@eam *6
2+
CALLP
addr24 *7
4
*1: 4 when a branch is made; otherwise, 3
*2: 3 x (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table A.5-1 "Execution cycle counts in each addressing mode" and Table A.5-2 "Cycle count
correction values for counting execution cycles" for information on (a) to (d) in the table.
650
#
RG
B
*1
0
0
Branch on (Z) = 1
*1
0
0
Branch on (Z) = 0
*1
0
0
Branch on (C) = 1
*1
0
0
Branch on (C) = 0
*1
0
0
Branch on (N) = 1
*1
0
0
Branch on (N) = 0
*1
0
0
Branch on (V) = 1
*1
0
0
Branch on (V) = 0
*1
0
0
Branch on (T) = 1
*1
0
0
Branch on (T) = 0
*1
0
0
Branch on (V) nor (N) = 1
*1
0
0
Branch on (V) nor (N) = 0
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
*1
0
0
Branch on (C) or (Z) = 1
*1
0
0
Branch on (C) or (Z) = 0
*1
0
0
Unconditional branch
2
0
0
word (PC) <-- (A)
3
0
0
word (PC) <-- addr16
3
1
0
word (PC) <-- (ear)
4+(a)
0
(c)
word (PC) <-- (eam)
5
2
0
word (PC) <-- (ear), (PCB) <-- (ear+2)
6+(a)
0
(d)
word (PC) <-- (eam), (PCB) <-- (eam+2)
4
0
0
word (PC) <-- ad24 0-15, (PCB) <-- ad24 16-23
6
1
(c)
word (PC) <-- (ear)
7+(a)
0
2 x (c) word (PC) <-- (eam)
6
0
(c)
word (PC) <-- addr16
7
0
2 x (c) Vector call instruction
10
2
2 x (c) word (PC) <-- (ear)0-15, (PCB) <-- (ear)16-23
11+(a)
0
*2
word (PC) <-- (eam)0-15, (PCB) <-- (eam)16-23
10
0
2 x (c) word (PC) <-- addr0-15, (PCB) <-- addr16-23
Operation
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