Bit Timing Register (Btr) - Fujitsu MB90895 Series Hardware Manual

16.3.5

Bit timing register (BTR)

The bit timing register (BTR) sets the prescaler and bit timing.Set this after halting the
bus (CSR: HALT = 1).
I Bit timing register (BTR)
R/W : Read/Write
X : Undefined
: Unused
Table 16.3-7 Function of bit timing register (BTR)
bit0
to
bit5
bit6,
bit7
bit8
to
bit11
bit12
to
bit14
Note:
Set the bit timing register (BTR) after halting the bus (CSR: HALT = 1). After setting the bit timing
register (BTR), write 0 to the HALT bit in the control status register to cancel the bus halt.
Figure 16.3-9 Bit timing register (BTR)
bit 15 14 13
TS2.2 TS2.1 TS2.0
R/W R/W
7 6 5
RSJ1 RSJ0 PSC5
R/W R/W R/W
Bit name
PSC5 to 0: These bits divide the frequency of the system clock to
prescaler setting bit 5 determine the time quantum (TQ) of the CAN controller.
to 0
RSJ1 to 0: These bits set the resynchronous jump width (RSJW).
resynchronous jump
width setting bits 1, 0
TS1.3 to 1.0: These bits set the time of time segment 1 (TSEG1).
time segment 1 setting Time segment 1 is equivalent to propagation segment
bits 3 to 0 (PROP_EG) and phase buffer segment 1 (PHASE_SEG1)
based on CAN specifications.
TS2.2 to 2.0: These bits set the time of time segment 2 (TSEG2).
time segment 2 setting Time segment 2 is equivalent to phase buffer segment 2
bits 2 to 0 (PHASE_SEG2) based on CAN specifications.
12 11 10 9
TS1.3 TS1.2 TS1.1
R/W R/W R/W R/W
4 3 2 1
PSC4 PSC3 PSC2 PSC1
R/W R/W R/W R/W
Function
CHAPTER 16 CAN controller
8 Reset value
TS1.0
X 1 1 1 1 1 1 1
B
R/W
0 Reset value
PSC0
1 1 1 1 1 1 1 1
B
R/W
495