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CHAPTER 14 UART0
G
Transmission
• Data to transmit is written to serial output data register 0 (SODR0) with the transmit data write flag bit
(SSR0: TDRE) containing "1".
• Transmission starts when the transmission enable bit (SCR0:TXE) in the serial control register is set to
"1"with the data to transmit written.
• The transmit data write flag bit (SSR0: TDRE) is temporarily cleared to "0" when data to transmit is
written to the serial output data register.
• The transmit data write flag bit (SSR0: TDRE) is set back to "1" when data to transmit is transferred
from serial output data register 0 (SODR0) to the transmission shift register.
• If the transmission interrupt enable bit (SSR0: TIE) contains "1", a transmission interrupt request is
generated when the transmit data write flag bit (SSR0: TDRE) is set to "1".During interrupt processing,
the next data to transmit can be written to serial output data register 0 (SODR0).
G
Reception
• Reception is always performed while it is enabled (SCR0: RXE = 1).
• Upon detection of the start bit in received data, the UART0 uses serial input data register 0 (SIDR0) to
receive one frame of data according to the data format set in serial control register 0 (SCR0).
• Upon completion of receiving one frame of data, the receive data load flag bit (SSR0: RDRF) is set to "1".
• To read received data, check the state of the error flag in the serial status register (SSR0) after receiving
one frame of data and, if the data has been received normally, read the received data from serial input
data register 0 (SSR0).When a reception error occurs, perform error handling.
• When received data is read, the receive data load flag bit (SSR0: RDRF) is cleared to "0".
G
Start bit detection method
To detect the start bit, make the following settings:
• Immediately before the communication period, be sure to set the communication line to H (add the mark
level).
• Enable reception (RXE=H) while the communication line remains at the mark level (H).
• Do not enable reception (RXE = H) except during the communication period (excluding the mark level)
• After detection of the stop bit (after the RDRF flag is set to 1), disable reception (RXE = L) while the
communication line remains at the mark level (H).
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