Fujitsu MB90895 Series Hardware Manual page 192

CHAPTER 4 I/O PORT
I Block Diagram of Pins of Port 3 (General-purpose I/O Port)
Port data register (PDR)
PDR read
PDR write
Port direction register (DDR)
DDR write
DDR read
Standby control Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
I Registers for Port 3
• The registers for port 3 are PDR3 and DDR3.
• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.5-2 shows the correspondence between registers and pins for port 3.
Table 4.5-2 Correspondence between Registers and Pins for Port 3
Port Name
port 3
*:MB90F897 has neither P35 nor P36.
174
Figure 4.5-1 Block Diagram of Pins of Port 3
Resource input
Output latch
Direction latch
Bits of Related Registers and Corresponding Pins
PDR3, DDR3 bit7
Corresponding pin P37
Resource output
Resource output
acceptance
Standby control (SPL=1)
bit6 bit5 bit4 bit3
−
P36* P35* P33
Pch
Pin
Nch
bit2 bit1 bit0
P32 P31 P30