Fujitsu MB90895 Series Hardware Manual page 578

CHAPTER 17 Address Match Detecting Function
Table 17.3-1 Functions of Address Detection Control Register (PACSR)
bit0
bit1
bit2
bit3
bit4
to
bit7
560
bit name
Reserved: reserved bit Always set this bit to "0".
AD0E: The address match detection operation with the detect address
Address match detection setting register 0 (PADR0) is enabled or disabled.
enable bit 0 When set to "0": Disables the address match detection
operation.
When set to "1": Enables the address match detection
operation.
•
Reserved: reserved bit Always set this bit to "0".
AD1E: The address match detection operation with the detect address
Address match detection setting register 1 (PADR1) is enabled or disabled.
enable bit 1 When set to "0": Disables the address match detection
operation.
When set to "1": Enables the address match detection
operation.
•
Reserved: reserved bit Always set this bit to "0".
Function
When the value of detect address setting register 0 (PADR0)
matches with the value of address latch at enabling the
address match detect operation (AD0E = 1), the INT9
instruction is immediately executed.
When the value of detect address setting registers 1
(PADR1) matches with the value of address latch at enabling
the address match detection operation (AD0E = 1), the INT9
instruction is immediately executed.