Serial Status Register 1 (Ssr1) - Fujitsu MB90895 Series Hardware Manual

15.3.3

Serial status register 1 (SSR1)

The serial status register 1 (SSR1) checks the transmission/reception status and error
status and enables/disables interrupts.
I Serial status register 1 (SSR1)
15 13
14
R R R
R/W : Reaad/Write
R : Read only
: Reset value
Figure 15.3-4 Serial status register 1 (SSR1)
12 11 10 9 8
R R R/W R/W R/W
bit8
TIE
0
1
bit9
RIE
0
1
bit10
BDS
0
1
bit11
TDRE
0
1
bit12
RDRF
0
1
bit13
FRE
0
1
bit14
ORE
0
1
bit15
PE
0
1
Reset value
00001000
B
Transmission interrupt generating enable bit
Transmission interrupt generating disabled
Transmission interrupt generating enabled
Reception interrupt generating enable bit
Reception interrupt generating disabled
Reception interrupt generating enabled
Transmission direction select bit
LSB first (transmission from lowest bit)
MSB first (transmission from uppermost bit)
Transmission data writing flag bit
With transmission data (transmission data writing disabled)
Without transmission data (transmission data writing enabled)
Reception data load flag bit
Without reception data
With reception data
Framing error flag bit
Without framing error
With framing error
Overrun error flag bit
Without overrun eeror
With overrun error
Parity error flag bit
Without parity error
With parity error
CHAPTER 15 UART1
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