Fujitsu MB90895 Series Hardware Manual page 475

G
Baud rate (clock mode)
The baud rate in the synchronous mode is generated by dividing the output clock of the communication
prescaler by 1, 2, 4, 8, 16 and 32.The division ratio is set by the clock input source select bits (SMR1
register bit 5 to 3: CS2 to CS0).
Table 15.5-3 Baud Rate (Clock Synchronous)
CS2 CS1
0 0
0 0
0 1
0 1
1 0
1 0
φ:Machine clock
div: Division ratio based on communication prescaler
CS0 CLK Synchronous
0 2Mbps
1 1Mbps
0 500kbps
1 250kbps
0 125kbps
1 62.5kbps
frequency
CHAPTER 15 UART1
Calculation
(φ/ div) / 1
(φ / div) / 2
(φ/ div) / 4
(φ/ div) / 8
(φ/ div) /16
(φ/ div) /32
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