Fujitsu MB90895 Series Hardware Manual page 149

Table 3.8-1 Functions of low-power consumption mode control register (LPMCR)
bit name
bit0 Reserved: reserved bit
bit1 CG1, CG0:
bit2 CPU halt cycle count
select bits
bit3 TMD:
watch mode bit
bit4 RST:
Internal reset signal
generation bit
bit5 SPL:
setting pin state bit
bit6 SLP:
sleep mode bit
bit7 STP:
stop mode bit
Notes: • To set the low power consumption mode control register (LPMCR) to enter a low power consumption
mode, use the instructions listed in Table 3.8-2 "Instructions at Transition to Low-power Consumption
Mode".
• The low-power consumption mode transition instruction in Table 3.8-2"Instructions used for change to
low-power consumption mode" must always be followed by an array of instructions highlighted by a
line below.
MOV
NOP
NOP
JMP
MOV
The devices does not guarantee its operation after returning from the low-power
consumption mode if you place an array of instructions other than the one enclosed in
the dine.
Always set this bit to "0".
These bits are used to set the halt cycle count of the CPU clock in the CPU intermittent operation
mode.
• Any reset causes the bit to return to the reset value.
Shift to watch mode or timebase timer mode
When the bit is set to "0": The CPU enters the watch mode.
When the bit is set to "1": No effect.
The bit is set to "1" when a reset or interrupt occurs.
Read: "1" is always read.
generating software reset
When the bit is set to "0": An internal reset signal for three machine cycles is generated.
When the bit is set to "1": No effect.
Read: "1" is always read.
The bit is used to set the state of input/output pins after transition to the stop mode, watch mode,
or timebase timer mode.
When the bit is set to "0": The current level of input/output pins is held.
When the bit is set to "1": The I/O pins enter a high impedance state.
• The bit is initialized to "0" at a reset.
Shift to sleep mode
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the sleep mode.
• The bit is initialized to "0" when a reset or external interrupt occurs.
• When the STP and SLP bits are set to "1" at the same time, the STP bit supersedes the SLP bit,
causing a transition to stop mode.
Transiting to the stop mode.
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the stop mode.
Read: "1" is always read.
• The bit is initialized to "0" when a reset or external interrupt occurs.
LPMCR,#H'XX ; The low-power consumption mode transition instruction
in Table 3.8-2
$+3 ; jump to next instruction
A,#H'10 ; any instruction
Function
CHAPTER 3 CPU
131