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2
I EI
OS Status Register (ISCS)
2
The EI
pointer and I/O address pointer, transfer data format (byte/word), and transfer direction.
Figure 3.5-13 shows the bit configuration of the EI
7
6
5
R/W
R/W
R/W
R/W: Read/Write
X: Undefined
*1: The buffer address pointer changes only in the lower 16 bits and enables in increment only.
*2: I/O address pointer enables in increment only.
OS status register (ISCS) is an 8-bit register that sets the method to update the buffer address
Figure 3.5-13 Configuration of EI
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
2
OS status register (ISCS).
2
OS Status Register (ISCS)
Reset value
X X X X X X X X
B
bit0
SE
2
El
OS terminate control bit
0
Not termination by the termination request from a peripheral resource
1
Termination by the termination request from a peripheral resource
bit1
DIR
Data transfer direction specification bit
0
I/O address pointer buffer address pointer
1
Buffer address pointer I/O address pointer
bit2
BF
BAP updating/fixed select bit
0
Buffer address pointer is updated after data transfer.
1
Buffer address pointer is not updated after data transfer.
bit3
BW
Transfer data length specification bit
0
Byte
1
Word
bit4
IF
IOA updating/fixed select bit
0
I/O address pointer is updated after data transfer.
1
I/O address pointer is updated after data transfer.
bit7
bit6
bit5
Reserved
Reserved
Reserved
0
0
0
Always write to this bit "0".
CHAPTER 3 CPU
*1
*2
Reserved bit
83
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