Reception Interrupt Generation And Flag Set Timing - Fujitsu MB90460 Series Hardware Manual

CHAPTER 17 UART
17.5.1

Reception Interrupt Generation and Flag Set Timing

The following are the reception interrupt causes: completion of reception (SSR0/SSR1:
RDRF) and occurrence of a reception error (SSR0/SSR1: PE, ORE, or FRE).
■ Reception Interrupt Generation and Flag Set Timing
Receive data is stored in input data register 1 (SIDR0/SIDR1) if a stop bit is detected (in operation mode 0
or 1) or the last bit of data is detected (in operation mode 2) during reception. If a reception error is
detected, the error flags (SSR0/SSR1: PE, ORE and FRE) are set, then the receive data flag (SSR0/SSR1:
RDRF) is set to "1". If one of the error flags is "1" in each mode, the SIDR0/SIDR1 register contains
invalid data.
●
Operation mode 0 (asynchronous, normal mode)
The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (PE,
ORE and FRE) are set.
●
Operation mode 1 (asynchronous, multiprocessor mode)
The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (ORE
and FRE) are set. Parity errors cannot be detected.
●
Operation mode 2 (synchronous, normal mode)
The RDRF bit is set when the last bit of receive data (D7) is detected. If a reception error is detected, the
error flag (ORE) is set. Parity and framing errors cannot be detected. Figure 17.5-1 below shows the
reception operation and flag set timing.
Receive data
(operation mode 0)
Receive data
(operation mode 1)
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
* : The PE flag cannot be used in mode 1
The PE and PRE flags cannot be used in mode 2
ST : Start bit
SP : Stop bit
A/D : Mode 2 (multiprocessor mode) address/data selection bit
●
Reception interrupt generation timing
When the RDRF, PE, ORE or FRE flag is set to "1" in the reception interrupt enable state (SSR0/SSR1:
RIE = 1), reception interrupt requests (#37 and #39) are generated.
488
Figure 17.5-1 Reception Operation and Flag Set Timing
ST
D0
ST
D0
D0
D1 D5 D6
D1 D6 D7
D1 D4
D7/P
SP
A/D
SP
D5 D6
D7
A reception interrupt occurs.