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CHAPTER 6 Watchdog timer
G
Checking reset factors
• The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can
be read after a reset to check the reset factors.
Note:
For details on the reset source bit, see Section 3.6 Reset.
Figure 6.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Watchdog timer block diagram]
[Minimum interval time] When clear WTE bit immediately before rising of counter clock.
Count clock a
2-division's value b
2-division's value c
Count enable
Reset signal d
[Minimum interval time] When clear WTE bit immediately after rising of counter clock.
Counter clear
Count clock a
2-division's value b
2-division's value c
Count enable
Reset signal
216
2-bit counter
a
Clock
2-division
selector
circuit
Count enable
WTE bit
output circuit
Count start
Counter clear
7
WTE bit clear
Count start
9
(Count clock cycle/2)
WTE bit clear
b
c
2-division
circuit
Count enable and clear
(Count clock cycle/2)
Watchdog reset generation
Watchdog reset generation
d
Reset
Reset circuit
signal
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