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CHAPTER 4 I/O PORT
G
Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state. The output buffer is set forcibly to "OFF" irrespective of the value of the DDR1.
Table 4.3-4 shows state of port 1 pins.
Table 4.3-4 State of Port 1 Pins
Pin Name
P10/IN0 to
P17/PPG3
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
To set that pin to high impedance which serves either as a peripheral resource or as a port in
stop mode, watch mode, or timebase timer mode, disable the output of the peripheral
resource, then set the STP bit to "1" or set the TMD bit to "0".Listed below are applicable
ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3
166
Normal
Sleep mode
Operation
General-
General-
purpose I/O
purpose I/O
ports
ports
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
Input cut off, and
General-purpose I/O
output becomes Hi-Z
ports
(Pull-up resistor
disconnected)
SPL=1
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