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CHAPTER 15 UART1
G
Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The division ratio of the machine clock is set by the division ratio select bits in the communication
prescaler control register (CDCR1 register bit 10 to 8: DIV2 to DIV0).
Table 15.5-1 Division Ratio Based on Communication Prescaler
MD
* div: Division ratio based on communication prescaler
G
Baud Rate (Asynchronous Mode)
The baud rate in the asynchronous mode is generated using output clock of the communication prescaler.
The division ratio is set by the clock input source select bits (SMR1 register bit 5 to 3: CS2 to CS0).
Table 15.5-2 Baud Rate (Asynchronous Mode)
456
DIV2
0
-
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
CS2
CS1
CS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
φ
:Machine clock frequency
div:Division ratio based on communication prescaler
DIV1
DIV0
-
-
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Asynchronous Mode (Start/Stop
Synchronous)
76,923bps
38,461bps
19,230bps
9,615bps
500kbps
250kbps
div*
Stops
1-frequency division
2-frequency division
3-frequency division
4-frequency division
5-frequency division
6-frequency division
7-frequency division
8-frequency division
Calculation
φ
/ div) / (8 × 13 × 2)
(
φ
/ div) / (8 × 13 × 4)
(
φ
/ div) /(8 × 13 × 8)
(
φ
/ div) / (8 × 13 × 16)
(
φ
/ div) / (8 × 2 × 2)
(
φ
/ div) / (8 × 2 × 4)
(
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