Fujitsu MB90895 Series Hardware Manual page 86

CHAPTER 3 CPU
Table 3.5-5 Correspondence between EI
Addresses (2/2)
ICS3
0
0
0
1
1
1
1
1
1
1
1
G
2
EI OS status bits (S1 and S0)
When the S1 and S0 bits are read at the termination of the EI
checked. At reset, the bit is set to "00
Table 3.5-6 "Relationships Between EI
2
the EI OS status bits (ICR: S1, S0) and the EI
Table 3.5-6 Relationships Between EI
S1
68
ICS2 ICS1 ICS0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
S0
0 0
0 1
1 0
1 1
2
OS Channel Select Bits and Descriptor
Channel to be Selected
5
6
7
8
9
10
11
12
13
14
15
".
B
2
OS Status Bits and EI
2
OS status.
2
OS Status Bits and EI
2
EI OS Status
2
When E OS in operation or not started
Stop state due to end of counting
Reserved
Stop state due to request from peripheral
Descriptor Address
000128
H
000130
H
000138
H
000140
H
000148
H
000150
H
000158
H
000160
H
000168
H
000170
H
000178
H
2
OS, the operating and end states can be
2
OS Status" shows the relationship between
2
OS Status