Fujitsu MB90895 Series Hardware Manual page 357

G
Selecting of DTP or external interrupt function
Whether the DTP function or the external interrupt function is executed depends on the setting of the
2
EI OS enable bit in the corresponding interrupt control register (ICR: ISE).
If the ISE bit is set to "1", the EI
If the ISE bit is set to "0", the EI
Notes: • All interrupt requests assigned to one interrupt control register have the same interrupt
level (IL2 to IL0).
• If two or more interrupt requests are assigned to one interrupt control register and EI
used for any of them, other interrupt requests cannot be used.
I DTP/External Interrupt Operation
The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 12.4-1.
Table 12.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt
Interrupt request flag bit
Interrupt request flag bit
Interrupt Factor
If the interrupt request signal from the DTP/external interrupt is output to the interrupt controller and the
2
EI OS enable bit in the interrupt control register (ICR: ISE) is set to "0", the interrupt processing is
executed. When this bit is set to "1", the EI
2
OS is enabled and the DTP function is executed.
2
OS is disabled and the external interrupt function is executed.
DTP/external interrupt
EIRR: ER7 to ER4, ER0
ENIR: EN7 to EN4, EN0
Input of valid edge/level to INT7 to INT4, RX pins
2
OS is executed.
CHAPTER 12 DTP/external interrupt
2
OS is
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