Table of Contents
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11.5
Precautions when Using Delayed Interrupt Generation Module...................................................... 327
11.6
Program Example of Delayed Interrupt Generation Module............................................................ 328
CHAPTER 12 DTP/external interrupt ............................................................................. 329
12.1
Overview of DTP/External Interrupt ................................................................................................. 330
12.2
Block Diagram of DTP/External Interrupt......................................................................................... 331
12.3
Configuration of DTP/External Interrupt........................................................................................... 333
12.3.1
DTP/external interrupt factor register (EIRR) ............................................................................. 334
12.3.2
DTP/external interrupt enable register (ENIR)............................................................................ 335
12.3.3
Detection Level Setting Register (ELVR) (High)......................................................................... 336
12.3.4
Detection Level Setting Register (ELVR) (Low) ......................................................................... 337
12.4
Explanation of Operation of DTP/External Interrupt ........................................................................ 338
12.4.1
External Interrupt Function ......................................................................................................... 341
12.4.2
DTP Function.............................................................................................................................. 342
12.5
Precautions when Using DTP/External Interrupt ............................................................................. 343
12.6
Program Example of DTP/External Interrupt Function .................................................................... 345
CHAPTER 13 8/10-bit A/D converter.............................................................................. 349
13.1
Overview of 8-/10-bit A/D Converter................................................................................................ 350
13.2
Block Diagram of 8-/10-bit A/D Converter ....................................................................................... 351
13.3
Configuration of 8-/10-bit A/D Converter ......................................................................................... 354
13.3.1
A/D Control Status Register (High) (ADCS: H)........................................................................... 356
13.3.2
A/D Control Status Register (Low) (ADCS: L) ............................................................................ 359
13.3.3
A/D Data Register (High) (ADCR: H).......................................................................................... 362
13.3.4
A/D Data Register (Low) (ADCR: L) ........................................................................................... 364
13.3.5
Analog input enable register (ADER) ......................................................................................... 365
13.4
Interrupt of 8-/10-bit A/D Converter ................................................................................................. 367
13.5
Explanation of Operation of 8-/10-bit A/D Converter ....................................................................... 368
13.5.1
Single-shot conversion mode ..................................................................................................... 369
13.5.2
Continuous conversion mode ..................................................................................................... 371
13.5.3
Pause-conversion mode ............................................................................................................. 373
13.5.4
13.5.5
A/D-converted Data Protection Function .................................................................................... 376
13.6
Precautions when Using 8-/10-bit A/D Converter ............................................................................ 379
CHAPTER 14 UART0 ....................................................................................................... 381
14.1
Overview of UART0 ......................................................................................................................... 382
14.2
Block Diagram of UART0................................................................................................................. 384
14.3
Configuration of UART0................................................................................................................... 387
14.3.1
Serial control register 0 (SCR0).................................................................................................. 389
14.3.2
Serial mode register 0 (SMR0) ................................................................................................... 391
14.3.3
Serial status register 0 (SSR0) ................................................................................................... 393
14.3.4
Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0)................... 395
14.3.5
Communication Prescaler Control Register 0 (CDCR0)............................................................. 397
14.3.6
Serial edge select register 0 (SES0) .......................................................................................... 398
14.4
Interrupt of UART0........................................................................................................................... 399
14.4.1
Generation of Receive Interrupt and Timing of Flag Set ............................................................ 401
2
OS Function ............................................................................................. 375
xi
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