Table of Contents
Advertisement
CHAPTER 8 16-bit reload timer
I Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait
state.When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation.The
pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select the level
(High or Low) of a rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the
TMR, continuing the TMR count operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.The pin output level select bit in the timer control status
register (TMCSR: OUTL) can be set to select the level (High or Low) of a toggle wave as the 16-bit reload
timer is started.
270
" to "FFFF
" during the
H
H
Advertisement
Table of Contents
