Fujitsu MB90895 Series Hardware Manual page 364

CHAPTER 12 DTP/external interrupt
Programming sample of DTP Function
Processing specification
• Channel 0 of Extended Intelligent I/O Service (EI
signal input to the INT4 pin.
• RAM data is output to port 0 by DTP processing (EI
Coding example
ICR06 EQU
DDR1 EQU
DDR5 EQU
ENIR EQU
EIRR EQU
ELVRL EQU
ELVRH EQU
ER4 EQU
EN4 EQU
;
BAPL EQU
BAPM EQU
BAPH EQU
ISCS EQU
IOAL EQU
IOAH EQU
DCTL EQU
DCTH EQU
;
;---------Main ptrogram-------------------------------------
CODE CSEG
START:
MOV
MOV
AND
MOV
;
;Data bank register (DTB) = 00H
;
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
;
CLRB
MOV
CLRB
SETB
MOV
OR
346
0000B6H
000011H
000015H
000030H
000031H
000032H
000033H
EIRR:0
ENIR:0
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
I:DDR1,#11111111B
I:DDR5,#00000000B
CCR,#0BFH
I:ICR06,#08H
BAPL,#00H
BAPM,#06H
BAPH,#00H
ISCS,#12H
IOAL,#00H
IOAH,#00H
DCTL,#0AH
DCTH,#00H
I:EN4
I:ELVRL,#00010000B ;INT4 sets "H" level detection.
I:ER4
I:EN4
ILM,#07H
CCR,#40H
2
OS) is started upon detection of the High level of the
2
OS).
;DTP/external interrupt control register
;Port 1 direction register
;Port 5 direction register
;DTP/external interrupt enable register
;DTP/external interrupt factor register
;Detection level setting: L
;Detection level setting: H
;INT4 interrupt request enable bit
;INT4 interrput request enable bit
;Buffer addresuu pointer loewr
;Buffer addresuu pointer middle
;Buffer addresuu pointer upper
2
;EI OS stasu register
;I/O address register lower
;I/O address register upper
;Data counter lower
;Data counter upper
;Stack pointer (SP),already initialized
;Setting output port in DDR1
;Setting input port in DDR5
;Interrupt disabled
;Interrupt level 0 (strongest) EI
;Channel 0
;Address for storing output data set
;(600 to 60A used)
H H
;Byte transmission, buffer address + 1,
;Fix I/O address,
;Transmission from memory to I/O
;Port 1 set as
;transfer destination address pointer
;Transfer count set to 10
;Disable INT4 in ENIR
;Interrupt request flag of INT4 in EIRR
;Clear
;Interrupt request enable of INT4 in ENIR
;Setting ILM in PS to level 7
;Interrupt enable
2
OS