Timing Limit Over Flag (Dq5) - Fujitsu MB90895 Series Hardware Manual

19.7.3

Timing Limit Over Flag (DQ5)

The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory
that the execution of the automatic algorithm has exceeded a prescribed time (the time
required for programming/erasing).
I Timing Limit Over Flag (DQ5)
Table 19.7-7 "State Transition of Timing Limit Over Flag (State Change at Normal Operation)" and
Table 19.7-8 "State Transition of Timing Limit Over Flag (State Change at Abnormal Operation"
give the state transition of the timing limit over flag.
Table 19.7-7 State Transition of Timing Limit Over Flag (State Change at Normal Operation)
Programming
Operating State
→
Completed
→
DQ5 0 DATA:5
Table 19.7-8 State Transition of Timing Limit Over Flag (State Change at Abnormal Operation
Operating
Programming
State
DQ5
G
At programming and chip/sector erasing
• If a read access is made after starting the automatic algorithm for programming or chip /sector
erasing and it is within a prescribed time (the time required for programming/erasing), the
timing limit over flag (DQ5) outputs 0. If it exceeds the prescribed time, the timing limit over
flag (DQ5) outputs 1.
• The timing limit over flag (DQ5) can be used to identify the success or failure of programming/
erasing, regardless of whether the automatic algorithm is in progress or terminated. If the
automatic algorithm by the data polling or the toggle bit function is in execution when the
timing limit over flag (DQ5) outputs 1, programming can be identified as a failure.
• For example, when 1 is set to the flash memory address with 1 set the flash memory,
programming fails. In this case, the flash memory will be locked and the automatic algorithm
will not complete. Therefore, no valid data is output from the data polling flag (DQ7). Also, the
toggle bit flag (DQ6) does not stop the toggle operation and exceeds the time limit, causing the
timing limit over flag (DQ5) to output 1. This state means that the flash memory is not being
used correctly; it does not mean that the flash memory is faulty. When this state occurs,
execute the reset command.
Chip and
Sector Erasing
→
Completed
→
0 1
Chip and
Sector Erasing
1 1
CHAPTER 19 512 KBIT FLASH MEMORY
Sector Erasing
→
Wait for Sector
Erasing
→
Erasing
Suspended
Started (Sector being
Erased)
0 0
Sector Erasing Sector Erasing
→
being
Suspended
Suspended
Resume
(Sector not
(Sector being
being Erased)
Erased)
0 DATA:5
595