Fujitsu MB90895 Series Hardware Manual page 233

G
Clearing watchdog timer
• When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval
time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not
cleared within the interval time, it overflows and the CPU is reset.
• A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode)
clear the watchdog timer.
• During operation in the timebase timer mode or watch mode, the watchdog timer counter is cleared.
However, the watchdog timer remains in the activation state.
• Figure 6.4-2 shows relationship between clear timing and interval time of watch dog timer. The interval
time varies with the timing of clearing the watchdog timer.
CHAPTER 6 Watchdog timer
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