Fujitsu MB90895 Series Hardware Manual page 435

Non communication period
Marc level
SIN
(01010101 transmission)
B
RXE
Reception clock
Sampling clock
Reception clock(8-pulse)
Recognition of maicrocontroller side
(01010101 reception)
B
Keep in mind that the microcontroller cannot recognize input data (SIN) correctly if reception is enabled at
the following timing.
• Example of operation when reception is enabled (RXE = H) while the communication line remains at L
level
Non communication period
Mark level
SIN
(01010101 transmission)
B
RXE
Reception clock
Sampling clock
Recognition of microcontrol side
(10101010 reception)
ST recognition
B
PE,ORE,FRE
G
Stop Bit
During transmission, one bit or two bits can be selected.However, the receive side always detects only the
first bit.
G
Error detection
• In operation mode 0, parity, overrun, and frame errors can be detected.
• In operation mode 1, overrun and frame errors can be detected.But parity errors cannot be detected.
Figure 14.6-2 example of normal operating
Start bit
ST D1
D0 D2
Sampling clock is built from 1/16 divided of the reception clock.
ST D1
D0 D2
Figure 14.6-3 example of abnormal operation
Start bit
ST D1
D0 D2
D0 D2
D1 D3
Communication period
Data
D5
D3 D7
D4 D6
D3 D5 D7
D4 D6
Communication period
Data
D3 D5 D7
D4 D6
D4 D6 SP
D5 D7
Reception error generating
CHAPTER 14 UART0
Non communication period
Stop bit
SP
SP
Non communication period
Stop bit
SP
417