Renesas H8/38023S Manuals

Manuals and User Guides for Renesas H8/38023S. We have 1 Renesas H8/38023S manual available for free PDF download: Hardware Manual

Renesas H8/38023S Hardware Manual (697 pages)

8-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 4.21 MB

Table of Contents
31
Section 1 Overview

43
- Overview
  43
- Internal Block Diagram
  49
- Pin Arrangement and Functions
  51
  - Pin Arrangement
    51
  - Pin Functions
    61
Section 2 CPU

67
- Overview
  67
  - Features
    67
  - Address Space
    68
  - Register Configuration
    68
- Register Descriptions
  69
  - General Registers
    69
  - Control Registers
    69
  - Initial Register Values
    71
- Data Formats
  71
  - Data Formats in General Registers
    72
  - Memory Data Formats
    73
- Addressing Modes
  74
  - Effective Address Calculation
    76
- Instruction Set
  80
  - Data Transfer Instructions
    82
  - Arithmetic Operations
    84
  - Logic Operations
    85
  - Shift Operations
    86
  - Bit Manipulations
    88
  - Branching Instructions
    92
  - System Control Instructions
    94
  - Block Data Transfer Instruction
    95
- Basic Operational Timing
  97
  - Access to On-Chip Memory (RAM, ROM)
    97
  - Access to On-Chip Peripheral Modules
    98
- CPU States
  99
  - Overview
    99
  - Program Execution State
    101
  - Program Halt State
    101
  - Exception-Handling State
    101
- Memory Map
  102
- Application Notes
  108
  - Notes on Data Access
    108
  - Notes on Bit Manipulation
    110
  - Notes on Use of the EEPMOV Instruction
    116
Section 3 Exception Handling

117
- Overview
  117
- Reset
  117
  - Reset Sequence
    117
  - Interrupt Immediately after Reset
    118
- Interrupts
  119
  - Overview
    119
  - Interrupt Control Registers
    121
  - External Interrupts
    132
  - Internal Interrupts
    133
  - Interrupt Operations
    134
  - Interrupt Response Time
    139
- Application Notes
  140
Section 4 Clock Pulse Generators

145
- Overview
  145
  - Block Diagram
    145
  - System Clock and Subclock
    146
  - Register Descriptions
    147
- System Clock Generator
  148
- Subclock Generator
  153
- Prescalers
  155
- Note on Oscillators
  156
- Notes on H8/38124 Group
  160
Section 5 Power-Down Modes

161
- Overview
  161
  - System Control Registers
    164
- Sleep Mode
  168
  - Transition to Sleep Mode
    168
  - Clearing Sleep Mode
    169
  - Clock Frequency in Sleep (Medium-Speed) Mode
    169
- Standby Mode
  170
- Watch Mode
  174
- Subsleep Mode
  176
  - Transition to Subsleep Mode
    176
  - Clearing Subsleep Mode
    176
- Subactive Mode
  177
  - Transition to Subactive Mode
    177
  - Clearing Subactive Mode
    177
  - Operating Frequency in Subactive Mode
    177
- Active (Medium-Speed) Mode
  178
- Direct Transfer
  179
- Module Standby Mode
  183
  - Setting Module Standby Mode
    183
  - Clearing Module Standby Mode
    183
Section 6 ROM

185
- Overview
  185
  - Block Diagram
    185
- H8/38024 PROM Mode
  186
  - Setting to PROM Mode
    186
  - Socket Adapter Pin Arrangement and Memory Map
    186
- H8/38024 Programming
  189
  - Writing and Verifying
    189
  - Programming Precautions
    194
- Reliability of Programmed Data
  195
- Flash Memory Overview
  196
  - Features
    196
  - Block Diagram
    197
  - Block Configuration
    198
  - Register Configuration
    200
- Descriptions of Registers of the Flash Memory
  200
- On-Board Programming Modes
  206
  - Boot Mode
    206
  - Programming/Erasing in User Program Mode
    209
  - Notes on On-Board Programming
    210
- Flash Memory Programming/Erasing
  210
- Program/Erase Protection
  216
  - Hardware Protection
    216
  - Software Protection
    216
  - Error Protection
    217
- Programmer Mode
  217
  - Socket Adapter
    217
  - Programmer Mode Commands
    218
  - Memory Read Mode
    221
  - Auto-Program Mode
    224
  - Auto-Erase Mode
    226
  - Status Read Mode
    227
  - Status Polling
    229
  - Programmer Mode Transition Time
    230
  - Notes on Memory Programming
    230
- Power-Down States for Flash Memory
  231
Section 7 RAM

233
- Overview
  233
  - Block Diagram
    233
Section 8 I/O Ports

235
- Overview
  235
- Port 1
  237
  - Overview
    237
  - Register Configuration and Description
    237
  - Pin Functions
    242
  - Pin States
    243
  - MOS Input Pull-Up
    243
- Port 3
  244
  - Overview
    244
  - Register Configuration and Description
    244
  - Pin Functions
    249
  - Pin States
    250
  - MOS Input Pull-Up
    250
- Port 4
  251
  - Overview
    251
  - Register Configuration and Description
    251
  - Pin Functions
    253
  - Pin States
    254
- Port 5
  255
  - Overview
    255
  - Register Configuration and Description
    255
  - Pin Functions
    258
  - Pin States
    259
  - MOS Input Pull-Up
    259
- Port 6
  260
  - Overview
    260
  - Register Configuration and Description
    260
  - Pin Functions
    262
  - Pin States
    263
  - MOS Input Pull-Up
    263
- Port 7
  264
  - Overview
    264
  - Register Configuration and Description
    264
  - Pin Functions
    266
  - Pin States
    266
- Port 8
  267
  - Overview
    267
  - Register Configuration and Description
    267
  - Pin Functions
    269
  - Pin States
    269
- Port 9
  270
  - Overview
    270
  - Register Configuration and Description
    271
  - Pin Functions
    274
  - Pin States
    274
- Port a
  275
  - Overview
    275
  - Register Configuration and Description
    275
  - Pin Functions
    277
  - Pin States
    278
- Port B
  279
  - Overview
    279
  - Register Configuration and Description
    279
  - Pin Functions
    281
- Input/Output Data Inversion Function
  282
- Application Note
  285
  - The Management of the Un-Use Terminal
    285
Section 9 Timers

287
- Overview
  287
- Timer a
  288
  - Overview
    288
  - Register Descriptions
    290
  - Timer Operation
    293
  - Timer a Operation States
    294
  - Application Note
    294
- Timer C
  295
  - Overview
    295
  - Register Descriptions
    297
  - Timer Operation
    300
  - Timer C Operation States
    302
- Timer F
  303
  - Overview
    303
  - Register Descriptions
    306
  - CPU Interface
    313
  - Operation
    316
  - Application Notes
    319
- Timer G
  323
  - Overview
    323
  - Register Descriptions
    325
  - Noise Canceler
    330
  - Operation
    332
  - Application Notes
    337
  - Timer G Application Example
    341
- Watchdog Timer
  342
  - Overview
    342
  - Register Descriptions
    345
  - Timer Operation
    351
  - Watchdog Timer Operation States
    352
- Asynchronous Event Counter (AEC)
  353
  - Overview
    353
  - Register Configurations
    356
  - Operation
    365
  - Asynchronous Event Counter Operation Modes
    370
  - Application Notes
    370
Section 10 Serial Communication Interface

373
- Overview
  373
  - Features
    373
  - Block Diagram
    375
  - Pin Configuration
    376
  - Register Configuration
    376
- Register Descriptions
  377
  - Receive Shift Register (RSR)
    377
  - Receive Data Register (RDR)
    377
  - Transmit Shift Register (TSR)
    378
  - Transmit Data Register (TDR)
    378
  - Serial Mode Register (SMR)
    379
  - Serial Control Register 3 (SCR3)
    382
  - Serial Status Register (SSR)
    386
  - Bit Rate Register (BRR)
    390
  - Clock Stop Register 1 (CKSTPR1)
    396
  - Serial Port Control Register (SPCR)
    396
- Operation
  398
  - Overview
    398
  - Operation in Asynchronous Mode
    402
  - Operation in Synchronous Mode
    411
  - Multiprocessor Communication Function
    418
- Interrupts
  425
- Application Notes
  426
Section 11 10-Bit PWM

431
- Overview
  431
  - Features
    431
  - Block Diagram
    432
  - Pin Configuration
    433
  - Register Configuration
    434
- Register Descriptions
  434
- Operation
  438
  - PWM Operation Modes
    439
Section 12 A/D Converter

441
- Overview
  441
  - Features
    441
  - Block Diagram
    442
  - Pin Configuration
    443
  - Register Configuration
    443
- Register Descriptions
  444
  - A/D Result Registers (ADRRH, ADRRL)
    444
  - A/D Mode Register (AMR)
    444
  - A/D Start Register (ADSR)
    446
  - Clock Stop Register 1 (CKSTPR1)
    447
- Operation
  448
- Interrupts
  449
- Typical Use
  449
- A/D Conversion Accuracy Definitions
  453
- Application Notes
  455
  - Permissible Signal Source Impedance
    455
  - Influences on Absolute Precision
    455
  - Additional Usage Notes
    456
Section 13 LCD Controller/Driver

457
- Overview
  457
  - Features
    457
  - Block Diagram
    458
  - Pin Configuration
    460
  - Register Configuration
    460
- Register Descriptions
  461
  - LCD Port Control Register (LPCR)
    461
  - LCD Control Register (LCR)
    463
  - LCD Control Register 2 (LCR2)
    465
  - Clock Stop Register 2 (CKSTPR2)
    467
- Operation
  468
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)

477
- Overview
  477
  - Features
    477
  - Block Diagram
    478
  - Pin Description
    479
  - Register Descriptions
    479
- Individual Register Descriptions
  479
- Operation
  485
  - Power-On Reset Circuit
    485
  - Low-Voltage Detection Circuit
    486
Section 15 Power Supply Circuit (H8/38124 Group Only)

493
- When Using Internal Power Supply Step-Down Circuit
  493
- When Not Using Internal Power Supply Step-Down Circuit
  494
Section 16 Electrical Characteristics

495
Appendix A CPU Instruction Set

577
- Instructions
  577
- Operation Code Map
  585
- Number of Execution States
  587
Appendix B Internal I/O Registers

592
- Addresses
  592
- Functions
  597
- B.2 Functions
  597
Appendix C I/O Port Block Diagrams

658
- Block Diagrams of Port 1
  658
- Block Diagrams of Port 3
  661
- Block Diagrams of Port 4
  666
- Block Diagram of Port 5
  670
- Block Diagram of Port 6
  671
- Block Diagram of Port 7
  672
- Block Diagram of Port 8
  673
- Block Diagrams of Port 9
  674
- Block Diagram of Port a
  676
- Block Diagrams of Port B
  677
Appendix D Port States in the Different Processing States

680
Appendix E List of Product Codes

681
Appendix F Package Dimensions

685
Appendix G Specifications of Chip Form

689

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Renesas H8/38023S Manuals

Renesas H8/38023S Hardware Manual (697 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 10-Bit PWM

Section 12 A/D Converter

Section 13 LCD Controller/Driver

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)

Section 15 Power Supply Circuit (H8/38124 Group Only)

Section 16 Electrical Characteristics

Appendix A CPU Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Port States in the Different Processing States

Appendix E List of Product Codes

Appendix F Package Dimensions

Appendix G Specifications of Chip Form

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