Hitachi H8S/2633 Hardware Manual page 581

2. OS = 1 (DADR corresponds to T
a. CFS = 0 [base cycle = resolution (T) × 64]
t
f1
t
H1
t = t = t = · · · = t
f1 f2 f3
t + t + t
H1 H2 H3
b. CFS = 1 [base cycle = resolution (T) × 256]
t
f1
t
H1
t = t = t = · · · = t
f1 f2 f3
t + t + t
H1 H2 H3
)
H
1 conversion cycle
t
f2
t
H2
= T × 64
= t
f255 f256
+ · · · + t + t
H255 H256
Figure 14-4 (3) Output Waveform
1 conversion cycle
t
f2
t
H2
= T × 256
= t
f63 f64
+ · · · + t + t = T
H63 H64
Figure 14-4 (4) Output Waveform
t
H3
= T
H
t
H3
H
t
f255
t t
H255 H256
t
f63
t t
H63 H64
t
f256
t
f64
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