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Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
Description
0
Burst cycle comprises 1 state
1
Burst cycle comprises 2 states
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
Description
0
Max. 4 words in burst access
1
Max. 8 words in burst access
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): In advanced mode, these bits select the
memory interface for areas 2 to 5.
When DRAM space is selected, the appropriate area becomes the DRAM interface.
Bit 2
Bit 1
RMTS2
RMTS1
0
0
1
1
1
Note: When all areas selected in DRAM are 8-bit space, the PF2 pin can be used as an I/O port
and for BREQO and WAIT. When contiguous RAM is selected set the appropriate bus width
and number of access states (the number of programmable waits) to the same values for all
of areas 2 to 5. Do not set other than the above combinations.
Bit 0
RMTS0
Area 5
0
Normal space
1
Normal space
0
Normal space
1
DRAM space
1
Contiguous DRAM space
Description
Area 4
Area 3
DRAM space
(Initial value)
(Initial value)
Area 2
DRAM space
143
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