Hitachi H8S/2633 Hardware Manual page 562

13.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 13-11 shows this operation.
ø
Address
Internal write signal
TCNT input clock
TCNT
Figure 13-11 Contention between TCNT Write and Increment
TCNT write cycle by CPU
T1
TCNT address
N
T2
M
Counter write data
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