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TIOR1—Timer I/O Control Register 1
Bit
:
IOB3
Initial value
:
R/W
:
TGR1B I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
1052
7
6
IOB2
0
0
R/W
R/W
TGR1A I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
TGR1B is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR1B is
Capture input
input
source is
capture
TIOCB1 pin
register
Capture input
source is TGR0C
compare match/
input capture
H'FF22
5
4
IOB1
IOB0
0
0
R/W
R/W
TGR1A is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR1A is
Capture input
input
source is
capture
TIOCA1 pin
register
Capture input
source is TGR0A
compare match/
input capture
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of TGR0C
compare match/input capture
3
2
IOA3
IOA2
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
*: Don't care
TPU1
1
0
IOA1
IOA0
0
0
R/W
R/W
*: Don't care
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