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7.9
Write Data Buffer Function
The H8S/2633 Series has a write data buffer function in the external data bus. Using the write data
buffer function enables external writes and DMA single address mode transmission to be executed
in parallel with internal accesses. The write data buffer function is made available by setting the
WDBE bit in BCRL to 1.
Figure 7-38 shows an example of the timing when the write data buffer function is used. When
this function is used, if an external write and DMA single address mode transmission continues for
2 states or longer, and there is an internal access next, only an external write is executed in the first
state, but from the next state onward an internal access (on-chip memory or internal I/O register
read/write) is executed in parallel with the external write rather than waiting until it ends.
Internal address bus
Internal read signal
A23 to A0
External
space
write
HWR, LWR
D15 to D0
Figure 7-38 Example of Timing when Write Data Buffer Function is Used
T
1
CSn
On-chip memory read Internal I/O register read
External write cycle
T
T
2
W
Internal memory
External address
T
T
W
3
Internal I/O register address
199
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