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Hitachi H8S/2633 Hardware Manual page 752

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Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
Read ACKB in ICSR
No
of transmission
(ACKB = 1)?
Set TRS = 0 in ICCR
Read ICDR
Clear IRIC in ICCR
Figure 18-17 Flowchart for Slave Receive Mode (Example)
18.3.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 18.2.8, DDC
Switch Register (DDCSWR).
734
IRIC = 1?
Yes
End
Yes
End
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
[1]
[3] Test for end of transfer.
[4] Select slave receive mode.
[5] Dummy read (to release the SCL line).
[2]
[3]
[4]
[5]

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