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Hitachi H8S/2633 Hardware Manual page 323

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9.2
Register Descriptions
9.2.1
DTC Mode Register A (MRA)
Bit
:
Initial value
:
Unde-
R/W
:
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
Bit 6
SM1
SM0
0
1
0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
Bit 4
DM1
DM0
0
1
0
1
298
7
6
SM1
SM0
Unde-
fined
fined
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
4
DM1
DM0
Unde-
Unde-
fined
fined
3
2
MD1
MD0
Unde-
Unde-
fined
fined
1
0
DTS
Sz
Unde-
Unde-
fined
fined

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