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EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
Figure 7-37 (b) Example Idle Cycle Operation in RAS Down Mode (ICIS0=1)
7.8.2
Pin States in Idle Cycle
Table 7-8 shows pin states in an idle cycle.
Table 7-8
Pin States in Idle Cycle
Pins
A23 to A0
D15 to D0
CSn
CAS
AS
RD
HWR
LWR
DACKn
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.
198
DRAM space read
T
T
T
p
r
c1
Pin State
Contents of next bus cycle
High impedance
High*
High
High
High
High
High
High
External read
T
T
T
c2
1
1
DRAM space read
T
T
T
2
3
c1
Idle cycle
T
T
c1
c2
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