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TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
TCSR2—Timer Control/Status Register 2
TCSR3—Timer Control/Status Register 3
TCSR0
Bit
Initial value
R/W
TCSR1, TCSR3
Bit
Initial value
R/W
TCSR2
Bit
Initial value
R/W
Note: * Only 0 can be written to bits 7 to 5 ( to clear these flags).
:
7
6
5
CMFB
CMFA
OVF
:
0
0
0
R/(W) *
R/(W) *
R/(W) *
:
:
7
6
5
CMFB
CMFA
OVF
:
0
0
0
:
R/(W) *
R/(W) *
R/(W) *
:
7
6
5
CMFB
CMFA
OVF
:
0
0
0
R/(W) *
R/(W) *
R/(W) *
:
Bit 7: Compare match flag B
0
[Clearing]
(1) Reading CMFB then writing 0 to CMFB when CMFB=1
(2) When DTC is started by CMIB interrupt and DTC MRB DISEL bit is 0
1
[Setting]
When TCNT=TCORB
Bit 6: Compare match flag A
0
[Clearing]
(1) Reading CMFA then writing 0 to CMFA when CMFA=1
(2) When DTC is started by CMIA interrupt and DTC MRB DISEL bit is 0
1
[Setting]
When TCNT=TCORA
Bit 5: Timer overflow flag
0
[Clearing]
Reading OVF then writing 0 to OVF when OVF=1
1
[Setting]
When TCNT changes from H'FF to H'00
Bit 4: A/D trigger enable
0
A/D conversion start request by compare match A disabled
1
A/D conversion start request by compare match A enabled
Bits 3 to 0: Output select 3 to 0
OS3
OS2
0
0
No change at compare match B
1
0 output at compare match B
1
0
1 output at compare match B
1
Inverted output each compare match B (toggle output)
OS1
OS0
0
0
No change at compare match A
1
0 output at compare match A
1
0
1 output at compare match A
1
Inverted output each compare match A (toggle output)
H'FF6A
H'FF6B
H'FDC2
H'FDC3
4
3
2
ADTE
OS3
OS2
0
0
0
R/W
R/W
R/W
4
3
2
—
OS3
OS2
1
0
0
—
R/W
R/W
4
3
2
—
OS3
OS2
0
0
0
R/W
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
TMR0
TMR1
TMR2
TMR3
1013
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