Hitachi H8S/2633 Hardware Manual page 591

Reset Control/Status Register (RSTCSR)

Initial value :

Note: * Only 0 can be written, for flag clearing.

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal

reset signal caused by overflows.

Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details

see section 15.2.5, Notes on Register Access.

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from

H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.

[Clearing condition]

Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF

[Setting condition]

Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer

Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the

H8S/2633 Series if TCNT overflows during watchdog timer operation.

Reset signal is not generated if TCNT overflows*

Reset signal is generated if TCNT overflows

Note: * The modules within the H8S/2633 Series are not reset, but TCNT and TCSR within the

WDT are reset.

(Initial value)