Hitachi H8S/2633 Hardware Manual page 218

Full access Burst access
T T T T T T T
1 2 3 1 2 1 2
ø
Low address only changes
Address bus
CS0
AS
RD
Data bus
Read data Read data Read data
Figure 7-32 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)
192