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• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Electrical Characteristics. Note that the I
met with a system clock frequency of less than 5 MHz.
• The I
2
C bus interface specification for the SCL rise time t
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
Table 18-7 Permissible SCL Rise Time (t
t
cyc
IICX
Indication
0
7.5t
Standard
cyc
mode
High-speed
mode
1
17.5t
Standard
cyc
mode
High-speed
mode
• The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
shown in table 18-6. However, because of the rise and fall times, the I
specifications may not be satisfied at the maximum transfer rate. Table 18-8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t
fails to meet the I
BUFO
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
2
C bus interface monitors the SCL line and synchronizes
2
I
C Bus
Specification
(Max.)
1000 ns
300 ns
1000 ns
300 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either
in standard mode fail to satisfy the I
STASO
, as shown in table 25-11 in section 25,
cyc
2
C bus interface AC timing specifications will not be
is under 1000 ns (300 ns for high-
sr
(the time for SCL to go from low to V
sr
2
C bus interface, the high period of SCL is
) Values
Sr
Time Indication
ø =
ø =
ø =
5 MHz
8 MHz
10 MHz
1000 ns 937 ns
750 ns 468 ns 375 ns
300 ns 300 ns
300 ns 300 ns 300 ns
1000 ns 1000 ns 1000 ns 1000 ns 875 ns
300 ns 300 ns
300 ns 300 ns 300 ns
/t
. Possible solutions that should be
Sr
Sf
) exceeds
IH
ø =
ø =
ø =
16 MHz
20 MHz
25 MHz
300 ns
300 ns
700 ns
300 ns
and t
Scyc
2
C bus interface
2
C bus.
2
C bus interface
, as
cyc
737
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