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TIOR3H—Timer I/O Control Register 3H
Bit
:
IOB3
Initial value
:
R/W
:
TGR3B I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
*
1
*
*
Note: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
1048
7
6
IOB2
0
0
R/W
R/W
TGR3A I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
TGR3B is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR3B is
Capture input
input
source is
capture
TIOCB3 pin
register
Capture input
source is channel
4/count clock
H'FE82
5
4
IOB1
IOB0
0
0
R/W
R/W
TGR3A is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR3A is
Capture input
input
source is
capture
TIOCA3 pin
register
Capture input
source is channel
4/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
1
count-down*
3
2
IOA3
IOA2
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT4 count-up/
count-down
*: Don't care
TPU3
1
0
IOA1
IOA0
0
0
R/W
R/W
*: Don't care
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