Hitachi H8S/2633 Hardware Manual page 215

DMAC Single Address Mode and DRAM Interface

When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the

DACK signal. It also selects whether or not to perform burst access when accessing the DRAM

space in DMAC single address mode.

Burst access is performed on the basis of the address only, regardless of the bus master. The

DACK output level changes to Low afer the T

Figure 7-30 shows the DACK output timing for the DRAM interface when DDS=1.

Note: n = 2 to 5

Figure 7-30 DACK Output Timing when DDS=1 (Example Showing DRAM Access)

state in the case of the DRAM interface.