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SCR0—Serial Control Register 0
SCR1—Serial Control Register 1
SCR2—Serial Control Register 2
SCR3—Serial Control Register 3
SCR4—Serial Control Register 4
Bit
:
7
TIE
RIE
Initial value
:
0
R/W
:
R/W
R/W
Receive interrupt enable
0 Disable receive data full interrupt (RXI) requests and receive error interrupt (ERI) requests.*
1 Enable receive data full interrupt (RXI) requests and receive error interrupt (ERI) requests.
Note: * To cancel RXI and ERI interrupt requests, either clear the RDRF or FER, PER, or ORER flags after
Transmit interrupt enable
0 Disable transmit data empty interrupt (TXI) requests.
1 Enable transmit data empty interrupt (TXI) requests.
Note: To clear TXI interrupt requests, clear the TDRE flag to 0 after reading "1", or clear the
TIE bit to 0.
1018
6
5
4
TE
RE
MPIE
0
0
0
R/W
R/W
Multiprocessor interrupt enable
0 Multiprocessor interrupt disabled (normal receive operations)
[Clearing]
(1) Clear the MPIE bit to 0;
(2) When data MPB=1 is received.
1 Multiprocessor interrupt enabled*
Until data is received that the multiprocessor bit = 1, receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and SSR RDRF, FER, and ORER flags cannot be set.
Note: * On reception of receive data that includes MPB=0, the receive data is not sent from the RSR to
Receive enable
0 Disable receive operation.*
1 Enable receive operation.*
Notes: 1. Clearing the RE bit has no effect on the RDRF, FER, PER, or ORER flags.
2. Serial receiving starts on detection of the start bit when in async mode, or on detection of sync clock input in clock sync
mode.
Before setting the RE bit to 1, be sure to set the SMR to decide the receive format.
Transmit enable
0 Disable transmit operation.*
1 Enable transmit operation.*
2
Notes: 1. The SSR TDRE flag is set to 1 (fixed).
2. Transmission starts when, in this state, transmit data is written to TDR and the SSR TDRE flag is cleared to 0. Before
setting the TE bit to 1, be sure to set the SMR to decide the transmit format.
reading "1", or clear the RIE bit to 0.
3
2
1
TEIE
CKE1
0
0
0
R/W
R/W
R/W
Clock enable 1, 0
Bit 1
Bit 0
CKE1
CKE0
0
0
1
1
0
1
Notes: 1.
Initial value
2.
Clock output at same frequency as bit rate
3.
Clock input at 16 times frequency of bit rate
Transmit end interrupt enable
0 Transmit end interrupt (TEI) requests disabled*
1 Transmit end interrupt (TEI) requests enabled*
Note: * To cancel a TEI, clear SSR TDRE flag to 0 after reading TDRE=1, then either clear the TEND
flag to 0 or clear the TEIE bit to 0.
the RDR, and, on detection of receive errors, the SSR RDRF, FER and ORER flags are not set.
On reception of receive data that includes MPB=1, the SSR MPB bit is set to 1 and the MPIE bit
is automatically cleared to 0. If an RXI or ERI interrupt request occurs (when the SCR TIE or RIE
bit is set to 1), the FER and ORER flags can be set.
1
2
1
H'FF7A
H'FF82
H'FF8A
H'FDD2
H'FDDA
0
CKE0
0
R/W
Description
Async mode
Internal clock/SCK pin set as I/O port*
Clock sync mode
Internal clock/SCK pin set for sync clock output*
Async mode
Internal clock/SCK pin set for clock output*
Clock sync mode
Internal clock/SCK pin set for sync clock output
Async mode
External clock/SCK pin set for clock input*
Clock sync mode
External clock/SCK pin set for sync clock input
Async mode
External clock/SCK pin set for clock input*
Clock sync mode
External clock/SCK pin set for sync clock input
SCI0
SCI1
SCI2
SCI3
SCI4
1
1
2
3
3
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