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Hitachi H8S/2633 Hardware Manual page 281

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Figure 8-11 illustrates operation in normal mode.
Address T
A
Address B
A
Legend
Address
T
= L
A
A
Address
T
= L
B
B
Address
B
= L
+ SAIDE · (–1)
A
A
Address
B
= L
+ DAIDE · (–1)
B
B
Where :
L
= Value set in MARA
A
L
= Value set in MARB
B
N
= Value set in ETCRA
Transfer requests (activation sources) are external requests and auto-requests.
With auto-request, the DMAC is only activated by register setting, and the specified number of
transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be
selected. In cycle steal mode, the bus is released to another bus master each time a transfer is
performed. In burst mode, the bus is held continuously until transfer ends.
256
Transfer
SAID
DTSZ
· (2
· (N–1))
DAID
DTSZ
· (2
· (N–1))
Figure 8-11 Operation in Normal Mode
Address T
B
Address B
B

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