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LPWRCR—Low-Power Control Register
Bit
Bit
:
:
Initial value
Initial value
:
:
R/W
R/W
:
:
Low-speed ON flag
0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation
• When the SLEEP command is executed in sub-active mode, operation transfers to watch mode, or
• Operation transfers to high-speed mode after watch mode is canceled.
1 • When the SLEEP command is executed in high-speed mode, operation transfers to watch mode or
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or
• Operation transfers to sub-active mode immediately watch mode is canceled.
Note: * Always select high-speed mode when transferring to watch mode or sub-active mode.
Direct transfer ON flag
0 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers to sleep
mode, software standby mode, or watch mode.
• When the SLEEP command is executed in sub-active mode, operation transfers to sub-sleep mode or watch mode.
1 • When the SLEEP command is executed in high-speed mode or medium-speed mode, operation transfers directly to
sub-active mode, or transfers to sleep mode or software standby mode.
• When the SLEEP command is executed in sub-active mode, operation transfers directly to high-speed mode or
transfers to sub-sleep mode.
Note: * Always select high-speed mode when transferring to watch mode or sub-active mode.
1028
7
6
DTON
LSON
NESEL
0
0
R/W
R/W
R/W
Subclock enable
0 Subclock generation enabled.
1 Subclock generation disabled.
Noise elimination sampling frequency select
0 Sampling uses ø/32 clock.
1 Sampling uses ø/4 clock.
transfers to sleep mode, software standby mode, or watch mode.*
directly to high-speed mode.
sub-active mode.
watch mode.
H'FDEC
5
4
3
SUBSTP
RFCUT
0
0
0
R/W
R/W
Frequency multiplier
STC1
0
1
Note:
A system clock frequency multiplied by the
multiplication factor (STC1 and STC0) should not
exceed the maximum operating frequency defined
in section 25 Electrical Characteristics.
Oscillator circuit feedback resistor control bit
0 Feedback resistor ON when main clock
operating; OFF when not operation.
1 Feedback resistor OFF.
2
1
—
STC1
0
0
R/W
R/W
STC0
× 1 (initial value)
0
× 2
1
× 4
0
1
Do not set.
System
0
STC0
0
R/W
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