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TIOR0H—Timer I/O Control Register 0H
Bit
:
IOB3
Initial value
:
R/W
:
R/W
TGR0B I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
*
1
*
*
Note: 1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
7
6
IOB2
IOB1
0
0
R/W
R/W
TGR0A I/O Control
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
*
1
*
*
TGR0B is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR0B is
Capture input
input
source is
capture
TIOCB0 pin
register
Capture input
source is channel
1/count clock
H'FF12
5
4
IOB0
IOA3
0
0
R/W
R/W
TGR0A is
Output disabled
output
Initial output is 0
compare
output
register
Output disabled
Initial output is 1
output
TGR0A is
Capture input
input
source is
capture
TIOCA0 pin
register
Capture input
source is channel
1/count clock
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
1
count-down*
3
2
IOA2
IOA1
0
0
R/W
R/W
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*: Don't care
TPU0
1
0
IOA0
0
0
R/W
*: Don't care
1051
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