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18.3.6
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 18-12 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
SCL
SDA
IRIC
User processing
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
SDA
IRIC
User processing
728
7
8
7
8
8
8
Clear
IRIC
7
8
7
8
Figure 18-12 IRIC Setting Timing and SCL Control
2
C bus format, no wait)
9
A
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
2
C bus format, wait inserted)
9
A
Clear
Write to ICDR (transmit)
IRIC
or read ICDR (receive)
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
1
1
1
1
1
1
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