Hitachi H8S/2633 Hardware Manual page 259

Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the

activation source selected by the data transfer factor setting is ignored. If the activation source is

an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1

when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer

end interrupt request to the CPU.

The conditions for the DTE bit being cleared to 0 are as follows:

• When initialization is performed

• When the specified number of transfers have been completed

• When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason

When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the

activation source selected by the data transfer factor setting. When a request is issued by the

activation source, DMA transfer is executed.

The condition for the DTE bit being set to 1 is as follows:

• When 1 is written to the DTE bit after the DTE bit is read as 0

Bit 6—Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1.

Data transfer disabled

Data transfer enabled

Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0.

Data transfer disabled

Data transfer enabled

Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an

interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when

DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer

break interrupt request to the CPU or DTC.

A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt

handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.

(Initial value)