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has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
(5) Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeating steps (4) and (5). When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
Start condition issuance
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
RDRF
IRIC
ICDRS
ICDRR
User processing
Figure 18-9 Example of Slave Receive Mode Operation Timing (1)
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
Slave address
(MLS = ACKB = 0)
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
R/W
[5] ICDR read
9
1
2
Bit 7
Bit 6
Data 1
[4]
A
Interrupt
request
generation
Address + R/W
Address + R/W
[5] IRIC clearance
725
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