Advertisement
7.2.8
DRAM Control Register (DRAMCR)
Bit
:
RFSHE
Initial value
:
R/W
:
R/W
The DRAMCR is an 8-bit read/write register that selects DRAM refresh mode, the refresh counter
clock, and sets the refresh timer control.
The DRAMCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Bit 7—Refresh Control (RFSHE): This bit selects whether or not to perform refresh control.
When not performing refresh control, the refresh timer can be used as an interval timer.
Bit 7
RFSHE
Description
0
Do not perform refresh control.
1
Perform refresh control.
Bit 6—CBR Refresh Mode (CBRM): This bit selects whether CBR refresh is performed in
parallel with other external access, or only CBR refresh is performed.
Bit 6
CBRM
Description
0
Enables external access during CAS-before-RAS refresh.
1
Disables external access during CAS-before-RAS refresh.
Bit 5—Refresh Mode (RMODE): This bit selects whether or not to perform a self refresh in
software standby mode when performing refresh control (RFSHE=1).
Bit 5
RMODE
Description
0
Do not perform self-refresh in software standby mode.
1
Perform self-refresh in software standby mode.
7
6
CBRM
RMODE
0
0
R/W
R/W
5
4
CMF
CMIE
0
0
R/W
R/W
3
2
CKS2
CKS1
0
0
R/W
R/W
1
0
CKS0
0
0
R/W
(Initial value)
(Initial value)
(Initial value)
151
Advertisement
